Integrated circuit pins are susceptible to receiving electrostatic discharge (ESD) pulses during the assembling process, and in some instances during normal operation. Improper dissipation of electrostatic discharge pulses can result in the damage to the circuit components in the integrated circuit. Existing ESD protection circuits can prevent damage from electrostatic discharges but can create reliability problems during the normal operation of the integrated circuit. For example, a disadvantage of known ESD protection circuits is the possibility of the power to ground shortage during a fast power up condition where the power ramps up at a fast rate when applied to the power nodes of the chip. In addition, known ESD protection circuits may create reliability problems caused by high frequency noise of voltage supply and ground that may be present on a power supply and ground nodes or rails. Hence, ESD protection circuits can cause latch up and integrated circuit damage during normal operation of a chip.
FIG. 1 illustrates a known ESD protection circuit 100 that includes a resistor/capacitor (RC) block 102 including an RC circuit that is coupled with a chain of inverters 104. Diodes 106 and 108 are also coupled to the I/O pin 110. A shunt structure 112, in this example an NMOS transistor, is turned “on” to sink ESD discharge current to significantly decrease the integrated circuit ESD over voltage condition to avoid integrated circuit damage. The RC time constant of the RC block 102 is set to be a longer time and much larger typically than the rising time of an expected ESD pulse to provide enough time for the shunt structure 112 to be in the “on” condition.
However, during a power up event in the case of a fast power up condition or for high frequency power/ground noise, the large time constant for the RC circuit 102 may cause the short of the power rail node 114 to the ground node 116 through shunt structure 112 which may result in a latch up condition and damage to the integrated circuit. A smaller RC time constant could prevent the shunt structure 112 from seeking current (current spikes) but would make an ESD condition less defensible and not efficient.
Therefore, a need exists that overcomes one or more of the above problems.